1. Technical Field of the Invention
The present invention relates to a volatile memory cell circuit, and particularly to a memory cell circuit for a static random access memory device.
2. Background of the Invention
Static random access memory (SRAM) devices have been employed for decades to store electronic data. An SRAM device includes an array of memory cells organized into rows and columns of memory cells. An addressable word line is coupled to the memory cells in a distinct row of memory cells. The memory cells in a column of memory cells are coupled to an addressable pair of bit lines. Data is written to and read from a memory cell in the memory cell array by selecting a row of memory cells and accessing memory cells therein that are coupled to selected bit line pairs. The organization and operation of SRAM devices are well known in the art.
The conventional SRAM cell is a six transistor (6T) cell. Specifically, the SRAM includes a latch element formed by a pair of cross coupled inverters. The latch element stores a single bit of data, with the value of the data bit depending upon the state of the latch element. The conventional SRAM cell includes a pair of transmission or pass gate transistors coupled to the input of the cross-coupled inverters. The pass gate transistors provide access to the SRAM for reading and writing data. The 6T SRAM cell is well known in the art.
Over the years, attempts have been made to optimize the SRAM cell. Improvements have occurred primarily with respect to memory cell layout and/or fabrication techniques. Little changes, however, have been directed to reducing the circuit itself so as to reduce fabrication complexity.